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Virtual Address Mapping
The MIPS processor contains an array of Translation Lookaside Buffer (TLB) entries that map, or translate, virtual addresses to physical ones. Most memory accesses are first mapped by reference to the TLB. This permits the IRIX kernel to implement virtual memory for user processes, and permits it to relocate parts of the kernel itself. The translation scheme is summarized in the following sections and covered in detail in the hardware manuals listed under "Additional Reading" on page xxxix.
TLB Misses and TLB Sizes
Each TLB entry describes a segment of memory containing two adjacent pages. When the input address falls in a page described by a TLB entry, the TLB supplies the physical memory address for that page. The translated address, now physical instead of virtual, is passed on to the cache, as shown in Figure 1-1.
When the input address is not covered by any active TLB entry, the MIPS processor takes a "TLB miss" interrupt to an IRIX kernel routine. The kernel routine inspects the address. When the address has a valid translation to some page in the address space, the kernel loads a TLB entry to describe that page, and restarts the instruction.
The size of the TLB is important for performance. The size of the TLB in different processors is shown in Table 1-2.
Number of TLB Entries by Processor Type
| Processor Type | Number of TBL Entries |
|---|
| R3000 (not supported by IRIX 6.2) | 64 |
| R4x00 | 96 |
| R8000 | 384 |
| R10000 | 128 |
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